The present invention is directed to silicon products incorporating junctions designed to conduct current and methods of making such devices. More specifically the invention relates to bipolar devices providing low-power, high-speed performance.
Currently there are over one hundred types of semiconductor devices, many of which are based on the well known p-n junction. Strictly speaking the p-n junction is a bipolar device but, as a building block of much integrated circuit design, these devices are usually one-sided in that one side of the junction is more heavily doped than the other. The semiconductor diode, functionally a descendant of the vacuum tube, may be the most basic application of the junction. The bipolar transistor, essentially two p-n junctions in series, i.e., pnp or npn, has often been regarded as the technology of choice for high performance applications, especially high speed switching. With ever increasing performance demands as communications circuits reach toward and beyond 40 gigabit per second speeds, solutions are needed to reduce collector resistance and collector-to-substrate junction capacitance in bipolar transistors. See, for example, U.S. Pat. No. 4,929,996 which discloses a buried collector layer electrically connected to a vertical collector conductor, with base and emitter regions formed in the collector epitaxial material.
The present invention is directed to a device architecture and a process for fabricating a semiconductor device incorporating a p-n junction. In preferred embodiments of the invention, an integrated electronic device includes a substrate layer of semiconductor material having a major surface formed along a crystal plane. A first region of a first conductivity type is formed in the substrate layer. A semiconductor layer, formed on the first region, e.g., by epitaxial growth, includes a first portion of a second conductivity type and a second portion of the first conductivity type formed over the first portion. The first portion and the first surface region form a pn junction.
An integrated electronic device is also provided with a substrate layer of semiconductor material having a major surface formed along a crystal plane and a deposited semiconductor layer formed on the substrate layer. The deposited layer includes a first portion of a first conductivity type and a second portion of a second conductivity type formed over the first portion. The first portion is formed along a plane parallel to the major surface. A dielectric layer is positioned over the semiconductor layer with a contact via formed therein to provide an electrical path from the plane along which the first portion is formed to a region above the plane. A conductive layer provides an electrical path in the plane from the first portion to the contact via. In a preferred embodiment the deposited semiconductor layer is substantially monocrystalline and may be epitaxially grown.
In an exemplary construction of the invention the epitaxially grown layer includes a bipolar transistor collector of a first conductivity type and a bipolar transistor base of a second conductivity type formed over the collector and a portion extending from the major surface to the collector. A conductive layer extending between the major surface and the emitter provides electrical connection to the collector.
According to an associated method of fabricating a semiconductor device a substrate layer includes an upper-most surface formed along a first plane and a first doped region of a first conductivity type is formed above the first plane. A second doped region of a second conductivity type is formed over the first doped region resulting in formation of a p-n junction in a second plane above the first plane. An electrical connection is provided to the first doped region with a conductor formed between the first and second planes.